Why does the F-Tile JESD204C Altera® IP Design Example fail to compile when migrated from a previous version of the Quartus® Prime Pro Edition Software to version 24.3?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile JESD204C Altera® IP Design Example will fail to compile when migrated from any previous version of the Quartus® Prime Pro Edition Software to version 24.3.

1. In the Files tab under Project Navigator window, locate the ed_control IP file (…rtl/<data_path>/ip/j204c_f_<data path>_ss/j204c_f_<data path>_ss_ed_control.ip) .
2. Expand the directory and find the target module (…rtl/<data_path>/ip/j204c_f_<data path>_ss/j204c_f_<data path>_ss_ed_control/synth/j204c_f_<data path>_ss_ed_control.v)
3. Comment out the all “csr_tst_ctl_tst_control_error_inject” ports.