Why does the F-Tile PMA/FEC Direct PHY FPGA IP variant with the “RS-FEC Mode” parameter is set to either “FlexO RS(544,514) or “FlexO RS(528,514)” fail to simulate properly?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile PMA/FEC Direct PHY IP variant with the “RS-FEC Mode” parameter set to either “FlexO RS(544,514)" or "FlexO RS(528,514)” will fail to simulate correctly.

In simulation, the “rsfec_sf”, “rsfecstatus_rx_not_align”, and “rsfec_status_rx_not_locked” ports of the IP will always be 1’b1.

This problem does not affect the operation of the IP in hardware.

To workaround this problem in Quartus®  Prime Pro Edition Software version 24.3, add the following compile option to the simulation script for your selected simulator:

+define+ SKIP_SIM_MODEL_LOG2_MRK

For example, if using the QuestaSim* simulator, add the following line to the simulation script:

set USER_DEFINED_VERILOG_COMPILE_OPTIONS "+define+ SKIP_SIM_MODEL_LOG2_MRK"

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.