Why do I get simulation error “wr_data is X” for F-Tile Ethernet FPGA Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and 24.2, you may see an error “wr_data is X” during simulation for F-Tile Ethernet FPGA Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled. While running the simulation, this error occurs for the 25GE-1 variant with the “MII PCS only” Client Interface example design.

To work around this problem, perform the following steps: 

1. )    Navigate to <your_design_path>/example_testbench folder 
2. )    Open “basic_avl_tb_top.sv” testbench file 
3. )    Add ~20us delay for the de-assertion of "i_reconfig_reset" as shown below 
   
4. )    Run the simulation as explained in the Design Example User Guide.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.