Why does toggling p0_pin_perst_n_i fail to reset PCI Express* links in the Agilex™ 5 FPGA E-Series ES devices in the Quartus® Prime Pro Edition Software version 24.2?

For a PCIe link in a transceiver bank, there are two pins in the HVIO banks with an optional function as PCIe platform reset (PERST#) for the PCIe link in the bank. You can connect PERST# to either one of the reset pins. The reset pin, not used as PERST#, can be used as a generic HVIO signal. For example, if pin PIN_PERST_N_CVP_L1A_0 in Bank 5A is connected to PERST# for the PCIe link in Bank L1A, pin PIN_PERST_N_CVP_L1A_1 in Bank 5B can be assigned as a generic HVIO signal.

Due to a problem in the ES devices, assigning either of the two reset pins as PERST# fails to reset the PCIe link.

For the Agilex™ 5 FPGA E-series in the current Quartus® Prime software release, you must assign both p0_pin_perst_n_i and p0_pin_perst_n_1_i ports to the location of the reset pins in HVIO banks as shown in the following table. Connect PERST# to either one of the reset pins. The other reset pin, not used as PERST#, must be left floating at the board level. For example, for a PCIe link in GTS bank L1B, assign p0_pin_perst_n_i to pin PIN_PERST_N_CVP_L1B_0 and assign p0_pin_perst_n_1_i to pin PIN_PERST_N_CVP_L1B_1. If you connect PERST# to PIN_PERST_N_CVP_L1B_0, leave PIN_PERST_N_CVP_L1B_1 floating at the board level. Tie the i_gpio_perst0_n port to logic high.

You must assign weak pull-down to pin preset ports in the Quartus® Prime Pro Software setting file. 

• set_instance_assignment -name WEAK_PULL_DOWN ON -to < p0_pin_perst_n_i pin>
• set_instance_assignment -name WEAK_PULL_DOWN ON -to <p0_pin_perst_n_1_i pin>
   

This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.