Why is the HPS I2C bus routed through FPGA IOs not working on Agilex™ 5 SoC FPGA?

Due to a problem in the Quartus® Prime Pro Edition software version 24.1 and earlier, you may see the HPS I2C bus unresponsive when it is routed via FPGA IOs.

To work around the problem, register the output enable (OE) of SDA and SCL by a fast clock. Below is a sample implementation :

   reg hps_i2c*_scl_oe_reg ;

   reg hps_i2c*_sda_oe_reg ;

   always @ (posedge system_clk_100_internal) begin

       hps_i2c*_scl_oe_reg  = hps_i2c*_scl_oe;

       hps_i2c*_sda_oe_reg  = hps_i2c*_sda_oe;

   end

assign hps_i2c*_scl = hps_i2c*_scl_oe_reg  ? 1’b0: 1’bz;

assign hps_i2c*_sda = hps_i2c*_sda_oe_reg ? 1’b0: 1’bz;

This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition Software.