Article ID: 000099211 Content Type: Troubleshooting Last Reviewed: 10/06/2025

Fatal Error: Segment Violation: faulting address=(nil), PC=0x7fffef9076bc : 0x7fffef9076bc: db_cdb_sgate!CDB_SGATE_NODE::get_string_hpath(std::__cxx11::basic_string, std::allocator

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, you might see the error message at Analysis & Synthesis stage when using the inference-flow for Tensor-Mode DSPs with RTL that has too many pipeline stages between the result of the intermediate multipliers and their column addition, but otherwise has the correct structure for a tensor-mode DSPs.

Resolution

To work around this problem, fix the RTL to match the actual tensor mode operation, refer to the templates that are included in the Quartus® Prime Pro Edition Software, as shown below:

DSP Tensor Mode Templates

This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3. 

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