Why does the input ports of a RTL module tied to logic 0 when connected to the F-Tile Reference and System PLL Clocks FPGA IP out_refclk_fgt and out_systempll_clk ports when viewing RTL Analyzer in Sweep mode?

Prior to Quartus® Prime 23.3 (i.e. 23.2 and older), the RTL Viewer provides a way to view a register transfer level (RTL) graphical representation of the connections between modules. Starting from the 23.3 release, Intel® introduced the Design Netlist Infrastructure (DNI) as a major change to the Quartus Prime software. As part of this change, the Analysis and Elaboration stage comprises a series of checkpoints, i.e., Elaborated, Instrumented, Constrained, and Swept.

This issue only appears when opening the RTL Analyzer in the Swept checkpoint. The ports are connected when opening the RTL Analyzer in other modes (Elaborated, Instrumented, or Constrained).

The out_systempll_clk is unconnected on the output port of the F-Tile Reference and System PLL Clocks FPGA IP because the System PLL is inside the tile. Hence, the source and sink ports are inside the tile and are not visible to the user. Hence, any connections made to this port will be tied to logic 0.

For the out_refclk_fgt port, the connection for this is handled through the Support Logic Generation stage where a net will be generated to perform the connections to the tile accordingly. Similarly, any connections made to this port will be tied to logic 0 as the connection for the out_refclk_fgt port is already made to the tile.

As an example, in the F-Tile JESD204C FPGA IP Design Example, the output port ext_net_in_refclk_fgt_<port_num>_load_out of the systemclk_f instance is connected to the input port ext_net_in_refclk_fgt_6_load_in on the jesd204c_f_ed_rx_tx_auto_tiles instance when viewed in the RTL Analyzer in Sweep mode.

Reference:

2.1.1.4. F-Tile Reference and System PLL Clocks IP

https://www.intel.com/content/www/us/en/docs/programmable/683372/22-2-6-0-0/f-tile-reference-and-system-pll-clocks-ip-35070.html

4.2.1. Reference and System PLL Clock for your IP Design

https://www.intel.com/content/www/us/en/docs/programmable/714307/22-2-3-0-0/reference-and-system-pll-clock-for-your.html

Quartus® Prime Pro Edition User Guide: Design Compilation
1.3. Design Netlist Infrastructure

https://www.intel.com/content/www/us/en/docs/programmable/683236/24-1/design-netlist-infrastructure.html

Note: By default, the Instrumented and Constrained checkpoints are disabled but can be turned on by enabling the RTL Analysis Debug Mode.

To view the connections, you can use the Elaborated, Instrumented or Constrained checkpoint when opening the RTL Analyzer. The elaborated and constrained views are to see the connections that are made in the RTL files. The swept view shows only the connections that are relevant to the design. Any connections that are not used or are stuck at a constant are removed in Sweep view. More information on each checkpoint can be found in the Quartus® Prime Pro Edition User Guide: Design Compilation.

After the design netlist is processed through Support Logic Generation, these connections are implemented fully inside the tile and/or using tile ports. Hence, you do not need not be concerned with the missing connections for the ports in your module connected to the F-Tile Reference and System PLL Clocks FPGA IP.