Article ID: 000099113 Content Type: Product Information & Documentation Last Reviewed: 06/27/2024

Which Fast Simulation Macros are documented for the Agilex™ 7 F-Tile Hard IP?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

This KDB details the recent advancements in macro development to improve simulation speeds for the Agilex™ 7 F-Tile Ethernet IPs. Its purpose is to clarify the specific macros applicable to various IPs and their compatibility with different versions of the Quartus® Prime Pro Edition Software. 

Other Macros already detailed in existing documentation, ip scripts or design examples should continue to be used as is. In any other circumstance, you should not pro-actively add them to your design.

Resolution

This document provides an extensive overview, showing the macros applicable to each IP. This will help you quickly identify the appropriate macro for your simulation needs.

Fast Simulation Macros for the Agilex™ 7 F-Tile Hard IP

Related Products

This article applies to 4 products

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Intel Agilex® 7 FPGAs and SoC FPGAs I-Series
Intel Agilex® 7 FPGA F-Series Development Kits
Intel Agilex® 7 FPGA I-Series Development Kits

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