Why is the input port signal of IP instance is not inverted in Signal Tap after an upper-level port signal is directly inverted on the instance port?

In the Quartus® Prime Pro Edition Software, if you invert the upper-layer port signal to the port of an FPGA IP instance as follows:

module top (

  input clk,

  input reset,

  ...

);

  nco inst (  .clk (clk),  .reset_n (~reset) ... );

  ...

endmodule

you may see that the signal on the IP port captured by the Signal Tap remains the same as the upper-layer port signal, no signal inversion occurred.

The output of the instance will work as expected after the upper-layer reset is deasserted.

This is because the synthesis stage has merged the invert inside the FPGA IP with the invert outside the FPGA IP, and both have been optimized.