Why does simulation fail when using the F-Tile DisplayPort FPGA IP Design Example?

Due to a problem in the Quartus® Prime Pro Edition Software Version 24.1, simulation of the F-Tile DisplayPort FPGA IP Design Example will run for more than 24 hours before failing with the message “Simulation hanged”.

To workaround this problem, modify the simulation/rtl/tx_phy/dp_gxb_tx/agi_dp_tx_reconfig.sv as shown below in bold. 

            FSM_SRC_OUT_RESET9:
            begin
                dp_sip_tx_NIOS_pause_request    <= {MAX_LANE_COUNT{1'b0}};
                if (!dp_sip_tx_NIOS_pause_grant_sync)
                    fsm_state <= FSM_END;
            end

            FSM_END:
            begin
                if (!(|dp_sip_tx_reset_control_ack_sync))
                begin
                    dp_sip_tx_reset_control_select  <= {MAX_LANE_COUNT{1'b0}};
                    fsm_state <= FSM_IDLE;
                end
            end

This problem is fixed beginning with version 24.2 of the Quartus® Prime Pro Edition Software.