Article ID: 000098905 Content Type: Errata Last Reviewed: 11/18/2024

Why does a fitter error happen when two System PLLs are used in the same transceiver bank in the Agilex™ 5?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, you may see a fitter error below when multiple different protocol IPs and two System PLL are implemented in a single GTS transceiver bank.

    Critical Warning: Could not find XCVR clock for my_directphy_inst_1|my_directphy|g1.n.sys[0].n_channel_superset_ip_inst|n_channel_superset_top_wrapper|hal_top_wrapper_inst|hal_top_ip|one_lane_inst_0|one_lane_hal_top_p0|pldif_hal_top_inst|pldif_hal_top|pldif_hal_coreip_inst|gen_sm_ch4_pldif_inst.ch4_pldif_inst|x_std_sm_hssi_pld_chnl_dp_0|o_hio_user_tx_clk1_clk

    Error (332000): ERROR: Argument <node_object> is an object filter that matches no objects. Specify one matches only one object.

    Resolution

    There is no workaround for cases where both PCIe and non-PCIe protocols are used in the same transceiver bank and each requires a System PLL.

    This problem is fixed beginning with the Quartus Prime Pro Edition software version 24.2.