This error states that the fitter cannot place either 1 SM_HSSI_PLD_CHNL_DP or 1 IPFLUXTOP_UXTOP_WRAP and occurs due to congestion of shared clocking resources between the HSSI-to-core clocks of a corner GTS transceiver bank and some pins from the adjacent HVIO bank.
In the Agilex™ 5 architecture, each channel in the GTS transceiver bank has 4 multiplexers which can pass through any of the tx_clkout, tx_clkout2, rx_clkout and rx_clkout2 clock outputs to the core fabric. If all 4 of these clock outputs are enabled, then all 4 multiplexers will be used and therefore no available multiplexers remain.
These multiplexers are also shared with certain pins from the adjacent HVIO banks, namely the PLL Refclk 1 and PLL Refclk 2 pins, the SourceSync Clk1 and SourceSync Clk2 pins, and also the IOPLL outputs of the HVIO bank.
The problem arises when all 4 transceiver clock outputs are enabled, and 1 or more of the HVIO pins listed above are also used. This would mean 5 or more clock lines are enabled and there is only 4 muxes available, thus causing this congestion issue.
This problem only affects GTS transceiver banks which are directly adjacent to a HVIO bank.
This is a device limitation; therefore, there is no fix.
The only way to work around this problem is to limit the mux usage to 4, either by reducing the transceiver clock to core outputs or using a different HVIO pin or a different HVIO bank.