Why are there unexpected timing paths with HPS EMAC clocks in the timing report when HPS EMAC is routed to the FPGA?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and earlier, you may see unexpected timing paths in the timing report for EMAC clocks when HPS EMAC is routed to the FPGA.

The top entity below helps to understand the EMAC clocks,  "emac1_gtx_clk" and "user0_clock_clk" used in the design, where EMAC1 is routed to the FPGA:

To work around this problem, use the following SDC constraints:

set_false_path -fall_from emac1_gtx_clk -rise_to emac1_gtx_clk

set_false_path -fall_from emac1_gtx_clk -rise_to user0_clock_clk

The problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.