Article ID: 000098794 Content Type: Troubleshooting Last Reviewed: 06/13/2025

Why is the "[VITAL_NO_PORT_ON_TGEN] Missing port association" warning flagged in VHDL simulation for GTS AXI Streaming IP for PCI Express*?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

The warning message exists because a generic timing signal "tpd_datainglitch_dataout" is used without a port driving it.  

This warning can be safely ignored during simulation. 

 

Resolution

This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.

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