Article ID: 000098764 Content Type: Error Messages Last Reviewed: 05/20/2024

Why does the Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP 10M/100M/1G/2.5G/10G Ethernet Design Example fail during simulation when using the Cadence* Xcelium* tool?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
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    Description

    Due to a problem in the Quartus® Prime Pro Edition Software Version 23.3 and earlier, the 10M/100M/1G/2.5G/10G Ethernet Design Example for the Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP will fail when simulating using the Cadence* Xcelium* tool.

     

    Resolution

    This problem has been fixed starting in version 23.4 of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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