Why are the HPS GMII to RGMII Adapter FPGA IP outputs always stuck to 0 on Agilex™ 5 designs?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, the HPS GMII to RGMII Adapter FPGA IP is not functioning for designs targeting Agilex™ 5.

You may observe HPS GMII to RGMII Adapter FPGA IP outputs are always stuck to 0 and/or PHY is not receiving any packet from FPGA IO. This problem occurs when HPS XGMAC is routed to FPGA IO using the HPS GMII to RGMII Adapter FPGA IP.

 

A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.1. Download and install Patch 0.19 from the following links:

• Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 for Windows (.exe)
• Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 for Linux (.run)
• Readme for Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 (.txt)

The patches will enable HPS GMII to RGMII Adapter FPGA IP to perform basic network transmission at 10Mbps/100Mbps link rate. 1Gbps speed is not supported in this patch.
Additionally, for Linux OS, you must modify the Linux Device Tree description in <linux-socfpga folder>/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts> to specify mac-mode as “gmii” for the EMAC instance being used with the FPGA IO pins. In the example below, the HPS gmac1 is selected for routing to FPGA IO:

&gmac1 {
       status = "okay";
       phy-mode = "rgmii-id";
       mac-mode = "gmii";
       phy-handle = <&emac1_phy0>;

       max-frame-size = <9000>;

       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               emac1_phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
};

This problem is scheduled to be fix in a future release of the Quartus® Prime Pro Edition Software.

Embedded Peripherals IP User Guide
Updated for Quartus® Prime Design Suite: 24.1
Publication Content ID: 683130

Chapter: HPS GMII to RGMII Adapter Intel FPGA IP