Why does my link partner report RX bit errors from the F-Tile PMA/FEC Direct PHY FPGA IP variant when the “Tx tile Interface Fifo Mode” parameter is set to “Register”?

Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and newer, your link partner may report receiving bit errors from the F-Tile PMA/FEC Direct PHY FPGA IP when the Tx tile Interface Fifo Mode parameter is set to “Register”.

To work around this problem, perform the following reads and writes on the reconfig_pdp bus of the IP:

1. Read register 0x6000 for all channels of the IP.
2. Write bits [10:9] of the register to 2’b10. Leave all other bits of the register unchanged (perform a read modify write)

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.