Article ID: 000098383 Content Type: Troubleshooting Last Reviewed: 04/08/2024

Why do I see bit errors when internal serial loopback is enabled for the Agilex™ 7 FGT transceiver manual adaptation mode designs?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and earlier, the internal serial loopback enablement sequence for the Agilex™ 7 FGT transceiver manual adaptation mode is not optimal. You might observe an unexpectedly high bit error rate (BER) when an external signal is present on the receiver's input.

    Resolution

    To workaround this problem, before enabling the internal serial loopback, you can adopt one of the following two methods:

    1. Disconnect FGT RX from the external cable or module
    2. Drive the external source signal in tri-state or electrical idle 

    There is no plan to fix this problem in a future release of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs