Article ID: 000098343 Content Type: Compatibility Last Reviewed: 03/18/2024

Why does HPS SPI controller fail to support continuous data transfer?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a known limitation, HPS SPI controller can not support continuous data transfer.

  1. When the HPS SPI controller acts as an SPI primary and transfers more than one frame, it always toggles SSx_N between each frame; it can not make SSx_N stay low during the transmitting period.
  2. When the HPS SPI controller acts as an SPI secondary and receives more than one frame, the paired SPI primary must toggle SS_N between each frame. Otherwise, only the first frame would be handled by the HPS SPI secondary.

 

 

Resolution

When the HPS SPI controller works as a primary, and the paired SPI secondary requires the SS_N to keep low during the transfer, a HPS GPIO can be used as SS_N instead of the SPI controller's SS_N. The HPS GPIO software can make the GPIO stay low during the whole transfer period.

When the HPS SPI controller works as a secondary, the paired SPI primary must transfer the frames one by one with SS_N toggling between each frame.

Related Products

This article applies to 3 products

Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Cyclone® V FPGAs and SoC FPGAs