Why is the parameter ‘pll_slf_rst’ set to false when PLL auto reset is enabled in the PLL FPGA IP in Stratix® V/Arria® V/Cyclone® V devices?

In the Quartus® Prime Standard Edition Software version 23.1 and earlier, you might see the parameter pll_slf_rst is set to false under the Analysis & Synthesis section of the compilation report in designs targeting the Stratix® V/Arria® V/Cyclone® V devices, even though the PLL auto-reset feature is enabled in the PLL FPGA IP.

The PLL FPGA IP auto-reset feature in the Stratix® V/Arria® V/Cyclone® V devices is enabled during the Fitter stage. It does not rely on the RTL parameter pll_slf_rst. You can ignore pll_slf_rst in the Analysis & Synthesis section of the compilation report.

To check if PLL auto reset is enabled in the Quartus® Prime Standard Edition Software version 22.1 and earlier, follow these steps:

1. Open the instantiated PLL Intel® FPGA IP in MegaWizard.
2. Switch to Advanced Parameters tab.
3. Check the value of PLL Auto Reset parameter.

To check if PLL auto reset is enabled in the Quartus® Prime Standard Edition Software version 23.1, follow these steps:

1. Open the compilation report.
2. Open the PLL Usage Summary report under the Fitter section.
3. Check the value of IOPLL Self RST.