Why do I have large periphery to core timing violations in my Agilex™ 5 FPGA design?

Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, you might see large timing violations on paths from a register in an IO Cell to a register in the core. The problem occurs because the tool underestimates the delay between the periphery and the core.

This problem only occurs in designs targeting Agilex™ 5 FPGA devices. 

To work around this problem, use a Logic Lock Region to constrain the core register(s) close to the IO Cell. Alternative solutions are using a timing overconstraint or increasing the fitter's effort.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.