Description
During simulation, an IOPLL Intel® FPGA IP with dynamic reconfiguration enabled may fail to lock when the mgmt_clk port of the PLL Reconfig Intel FPGA IP is connected to an output clock of another IOPLL Intel® FPGA IP in Intel® Arria® 10 devices. This behavior is only seen during simulation and it doesn't appear in hardware.
Resolution
As a workaround, connect the mgmt_clk port on the PLL Reconfig Intel® FPGA IP to a free running clock.