Why can't I fit more than eight FGT PAM4 lanes with 64-bit PMA width using a single F-Tile PMA/FEC Direct PHY Intel® FPGA IP on Intel® Agilex® 7 F-Tile devices?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software v23.4, when configuring the Intel® Agilex® 7 F-tile PMA/FEC Direct PHY Intel® FPGA IP with more than 8 FGT PMA lanes, the IP Parameter editor shows a warning message instead of an error message. The design may fail the Intel® Quartus® Prime Pro Edition Software, Design Analysis stage.

To implement more than 8 PMA lanes with 64-bit PMA width, you can use multiple F-Tile PMA/FEC Direct PHY Intel® FPGA IP and limit the number of lanes in single F-Tile PMA/FEC Direct PHY Intel® FPGA IP to a maximum of eight. For example, if you wanted twelve channels, you could implement three instances of a four-channel F-Tile PMA/FEC Direct PHY Intel® FPGA IP.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.