Why does the design with multiple clocks defined on the same pin having Low Latency 100G Ethernet FPGA IP for Stratix® 10 Devices with AN/LT enabled generate MTBF failure message?

Due to a problem in the Quartus® Prime Pro Edition Software version 21.4 and earlier, you may see MTBF failure message because there are three profile clocks defined on the same clock output pin in the generated SDC file of the Low Latency 100G Ethernet FPGA IP for Stratix® 10 Devices with AN/LT enabled. 

Although there are set_false_path constraints to cut off unnecessary paths, set_false_path uses a wildcard that matches too many registers that are not intended, which causes STA synchronizer detection to be confused.

To work around this problem in the Quartus® Prime Pro Edition Software version 21.4 and earlier, remove the set_false_path entirely in the generated SDC file for designs using multiple clocks on the same output pin of the Low Latency 100G Ethernet FPGA IP for Stratix® 10 Devices with AN/ LT enabled.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.