Article ID: 000097912 Content Type: Troubleshooting Last Reviewed: 05/07/2025

Why do the signals (nodes) in the Signal Tap Logic Analyzer disappear?

Environment

    Intel® Quartus® Prime Standard Edition

Windows 11* Family, Windows® 10 family

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Description

Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 or earlier, the signals (nodes) initially displayed in the Signal Tap Logic Analyzer might disappear after the trigger occurs. This is because the checkbox in the "Hierarchy Display" GUI window becomes unchecked, causing the signals to be hidden.  This problem only occurs when running on Windows* OS.

Resolution

To work around the problem, manually enable the checkbox in the "Hierarchy Display" GUI window.

This problem is fixed beginning with the Quartus® Prime Standard Edition Software version 24.1.

 

Related Products

This article applies to 10 products

Intel® Cyclone® 10 LP FPGA
MAX® V CPLDs
Arria® V GZ FPGA
Cyclone® V FPGAs and SoC FPGAs
Stratix® IV FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
MAX® II CPLDs
Arria® II FPGAs
Intel® MAX® 10 FPGAs
Stratix® V FPGAs

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