Why are 100 Gbps Ethernet transceiver channels not visible in the transceiver toolkit for the Low Latency 100G Ethernet Intel® FPGA IP Core for the Intel® Stratix® 10 H-Tile devices?

Due to the auto adaptation module finite state machine (FSM) in the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example, the channel does not appear in the transceiver toolkit for the Intel® Quartus® Prime Pro Edition Software version 23.3 and earlier. The problem occurs when the Enable AN/LT and Auto-Adaption mode option is turned on in the IP wizard; the transceiver toolkit operation will be interrupted when the FSM turns on and off background calibration on the Intel® Stratix10® H-Tile devices. 

If the Enable AN/LT and Auto-Adaption mode is turned on, write 1'b1 to bit [12] of 0xXX325 register to hold the auto adaptation module FSM to an idle state before launching the transceiver toolkit so the transceiver channel appears in the transceiver toolkit. Close the transceiver toolkit and write 1'b0 to bit [12] of 0xXX325 register to re-start the auto adaptation module FSM so the system console doesn't hang.

Below are the steps to be followed while using the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP design example on H-Tile devices and turn on the Enable AN/LT and Auto-Adaption mode option.

1. In the system console, type cd hwtest to navigate to the TCL scripts folder.
2. Type source main.tcl to load the main.tcl file.
3. For multi-channel Low Latency 100G Ethernet Intel® FPGA IP design example,
   1. Execute command reg_write 0x325 0x1 for channel 0.
   2. Execute command reg_write 0x10325 0x1 for channel 1.
   3. Execute command reg_write 0x20325 0x1 for channel 2.
   4. Execute command reg_write 0x30325 0x1 for channel 3.
4. Launch the transceiver toolkit, then transceiver channels for 100 Gbps are seen.

Follow these steps after you have used the transceiver toolkit:

1. Close the transceiver toolkit.
2. For multi-channel Low Latency 100G Ethernet Intel® FPGA IP design example,
   1. Execute command reg_write 0x325 0x0 for channel 0.
   2. Execute command reg_write 0x1032 05x0 for channel 1.
   3. Execute command reg_write 0x20325 0x0 for channel 2.
   4. Execute command reg_write 0x30325 0x0 for channel 3.

The issue has been fixed in version 23.4 of the Intel® Quartus® Prime Pro Edition Software.