Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.4 and earlier, there are no ATS (Address Translation Service) Capability Registers in the Intel Agilex® 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP, which is a required feature for the CXL.io path to translate virtual address to physical address according to the Compute Express Link* (CXL) specification.
This problem will not be fixed in future releases of the Intel® Quartus® Prime Edition Software.
To work around this problem, implement additional RTL code by following the description in Intel Agilex® 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP User Guide as below:
IP allows you to add extended capabilities to PF1 starting at address 0xE00. The design example includes a null extended capability configuration register at offset 0xE00, which terminates the extended capability chain.
Refer to the following code example:
1. Open /hardware_test_design/common/ex_default_csr/ex_default_csr_avmm_slave.sv.
2. Add the ATS capability registers:
//ATS 00E00+00E04
reg [4:0] ats_stu;
reg ats_en;
//00E00 Capability Header
localparam EX_CAP_HEADER_ATS = 32'hE101000f;
//00E04 Control
//{ats_en,10'h0,ats_stu,16'h0020}
always @(posedge clk )
if (!reset_n) begin
ats_stu <= 5'b0;
ats_en <= 1'b0;
end else if (write && config_access)begin
case(address[20:0])
21'h00E04 : begin
ats_stu <= writedata[20:16];
ats_en <= writedata[31];
end
default ;
endcase
end
always @(posedge clk )
if (!reset_n) begin
readdata <= 32'h0;
end else if(read&&config_access)begin
case(address[20:0])
21'h00E00 : readdata <= EX_CAP_HEADER_ATS;
21'h00E04 : readdata <= {ats_en,10'b0,ats_stu,16'h0020} ;
default : readdata <= 32'hffff_ffff;
endcase
end