Article ID: 000097436 Content Type: Troubleshooting Last Reviewed: 06/18/2024

Why does the R-Tile FPGA IP for Compute Express Link* (CXL*) Type2 Design Example report timing violation when selecting PLD clk frequency as 475Mhz?

Environment

  • Intel® Quartus® Prime Pro Edition

    • OS Independent family

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    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the R-Tile FPGA IP for Compute Express Link* (CXL*) Type2 Design Example might report timing violation when selecting PLD clk frequency as 475MHz.

    Resolution

    This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. 

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

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