Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, you might see this error during Synthesis in the following scenario:
- You created an example design for the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP or External Memory Interfaces (EMIF) IP in an Intel Agilex® 7 M-series FPGA.
- You modified your project to create a new top-level which instantiates two instances of this example design.
- The project’s Quartus Settings File (.qsf) retains NoC group, bandwidth, or transaction size assignments from the original example design, including any -entity arguments for these assignments.
In this scenario, you may also see that these assignments are not visible in the NoC Assignment Editor.
Resolution
To work around this problem, edit the .qsf to remove all NOC_GROUP, NOC_READ_BANDWIDTH, NOC_WRITE_BANDWIDTH, NOC_READ_TRANSACTION_SIZE, and NOC_WRITE_TRANSACTION_SIZE assignments with the argument “-entity ed_synth”.