The ‘REMOVE_SRC_NIOS’ macro is handled for simulation speed up when enabled and supported in all F-Tile Ethernet FPGA Hard IP example design simulation scripts within the Quartus® Prime Pro Edition Software version 23.3, except for the Xcelium™ and Aldec Riviera simulation scripts.
When the F-Tile Ethernet FPGA Hard IP is used outside of the example design, it is important to assert resets upon startup and maintain them until acknowledgments are received. These procedures are not compatible with Xcelium and Aldec Riviera simulation tools.
There are specific limitations associated with the ‘REMOVE_SRC_NIOS’ macro:
- It does not support dynamic reconfiguration, Auto-negotiation (AN), and Link training (LT) features.
- Multiple rates with multiple ports are not supported.
- When using multiple ports, they must be reset altogether.
When you work with Xcelium or Aldec Riviera simulators, and you use the ‘REMOVE_SRC_NIOS’ macro, you may experience problems with TX and RX lanes which fail to come up.
For Xcelium and Aldec Riviera simulators, there is a workaround for Quartus® Prime Pro Edition Software version 23.3 to use the ‘SRC_SPEC_SPEED_UP‘ macro instead of the ‘REMOVE_SRC_NIOS’ macro.
For other simulators, the limitations and support of the ‘REMOVE_SRC_NIOS’ macro to other IPs are scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.