Article ID: 000096811 Content Type: Connectivity Last Reviewed: 11/12/2024

Why does the .pin file show a VREF voltage requirement against the VREFB pins when using Differential SSTL/HSTL/HSUL I/O standards in Agilex™ 7 devices?

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in Quartus® Prime Pro Edition Software version 23.2 and earlier, the .pin file incorrectly shows a VREF voltage of 0.6V against the VREFB pins when using Differential SSTL/HSTL/HSUL I/O standards in Agilex™ 7 devices. These I/O standards do not require an external VREF.

Resolution

You may ignore the external VREF voltage requirement if using Differential SSTL/HSTL/HSUL I/O standards.

This problem is fixed starting from Quartus® Prime Pro Edition Software version 24.1 

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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