Description
You may see the warning while compiling Agilex™ 7 FPGA M-Series EMIF IP.
Resolution
DQS clock name has to be *dqs_t and *dqs_c at the top module to associate DQS as clock signals.
For example
//inout [ 4:0] MEM0_DQS_P,
//inout [ 4:0] MEM0_DQS_N,
inout [ 4:0] MEM0_dqs_t,
inout [ 4:0] MEM0_dqs_c,
This problem is planned to be fixed in a future release of Quartus® Prime Pro Edition Software.