Why does the F-Tile Ethernet Hard IP Design Example fail to program when targeting the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile)?

Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, device programming will fail for the F-Tile Ethernet Hard IP Design Example when targeting the following Development kits:
DK-SI-AGI027FA (Power Solution 2: Not Intel® Enpirion® power solution)
DK-SI-AGI027FC (Power Solution 2: Not Intel® Enpirion® power solution)

To work around this problem, change the VID settings within the design examples.QSF file. The correct VID settings can be obtained from section 6.1 Add SmartVID Settings in the Quartus® Prime QSF file of the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide, found here: add-smartvid-settings-in-the-qsf-file.html

The correct VID settings are:
set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
set_global_assignment -name USE_CONF_DONE SDM_IO16
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ"
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888
set_global_assignment -name NUMBER_OF_SLAVE_DEVICE 1
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 62
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS

Ensure that no similar settings with different values exist in the QSF file.

This problem was fixed in version 25.1 of the Quartus® Prime Pro Edition Software.