Critical warning in the Quartus® Prime Pro Edition Software version 23.1 when compiling the F-Tile HDMI FPGA IP Design Example.

Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, there is a Quartus Tile Logic Generation(QTLG) Critical Warning when compiling the F-Tile HDMI FPGA IP Design Example as shown below:

critical warning: the block u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_50|rx_phy_1p500g|dphy_hip_inst|persystem0.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx with top level ports fmc_rx_n0, fmc_rx_p0 did not set the following parameters
critical warning: the block u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_50|rx_phy_1p500g|dphy_hip_inst|persystem1.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx with top level ports fmc_rx_n1, fmc_rx_p1 did not set the following parameters

There is no workaround for this problem.
 

This problem has been fixed starting with Quartus® Prime Pro Edition Software version 23.2.