Why do F-Tile variants with PTP and Tx PTP classifier enabled within the Ethernet Subsystem Intel® FPGA IP fail to compile when using the Synopsys* VCS simulator?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.2,  F-Tile variants with PTP and PTP packet classifier enabled within the Ethernet Subsystem Intel® FPGA IP will fail to compile when using the Synopsys* VCS simulator. 

This problem does not affect other supported simulators.

To workaround this problem, add the “-ignore initializer_driver_checks” switch to the USER_DEFINED_ELAB_OPTIONS section of the run_vcs.sh file found in the <example design project name>/example_testbench directory.

This problem was fixed in version 23.3 of the Intel® Quartus® Prime Pro Edition Software.