Why does the register still exist in the Resource Property Editor after I disable the “data by delay register” in the Native Fixed Point DSP Intel® Arria® 10 FPGA IP parameter?

Due to a problem with the Resource Property Editor in the Intel® Quartus® Prime Standard Edition Software version 18.1 and earlier, when you use Native Fixed Point DSP Intel®  Arria® 10 FPGA IP and disabled "data by delay register" in the parameter settings, you may still see the register in the Resource Property Editor. 

The IP is implemented correctly, which is not shown in the Resource Property Editor.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Standard Edition Software.