Description
Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 20.4, you may encounter a fitter issue while placing REFCLK sharing between IO48 tiles within the same banks in PHY Lite Interfaces Intel Agilex® 7 FPGA IP.
Resolution
These errors are due to a hardware limitation. The fitter didn't check the REFCLK location constraint because it assumes the REFCLK needs to be in the same tile.