Why does the HDMI IP have no video output when integrating the HDMI FPGA IP 2.0 TX and HDMI FPGA IP RX 2.1 into a design ?

Due to a problem in the Quartus® Prime Pro Edition Software versions 23.1 and earlier, no HDMI video output is displayed when integrating the HDMI FPGA IP 2.0 TX and the HDMI FPGA IP 2.1 RX into a design. 

This is because the module bitec_hdmi_measure_vid/bitec_hdmi_scramble/bitec_hdmi_split_add/bitec_hdmi_symb_delay has the same module name between the HDMI FPGA IP 2.0 and the HDMI FPGA IP 2.1, but the RTL code is different.

To work around this problem:

Rename the compilation library into a different name in the qip files for the HDMI FPGA IP 2.0 and the HDMI FPGA IP 2.1.

This problem is fixed beginning with version 23.4 of the Quartus® Prime Pro Edition Software.