Due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 22.4 and earlier, you might see this critical warning when including the FIFO Intel® FPGA IP in a Partial Reconfiguration (PR) design partition.
This warning can safely be ignored as long as the DCFIFO or SCFIFO IP instances have their reset port (aclr or sclr) enabled and that this reset is asserted prior to the design partition entering user mode.
This problem is scheduled to be addressed in a future release of the Intel® Quartus® Prime Pro Edition Software.