Article ID: 000094233 Content Type: Error Messages Last Reviewed: 06/04/2025

Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "*|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "*", is ignored. The initial condition is not guaranteed during partial reconfiguration

Environment

    Intel® Quartus® Prime Pro Edition
    FIFO Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® Prime Pro Edition Software versions 22.4 and earlier, you might see this critical warning when including the FIFO IP in a Partial Reconfiguration (PR) design partition.

Resolution

This warning can safely be ignored as long as the DCFIFO or SCFIFO IP instances have their reset port (aclr or sclr) enabled and that this reset is asserted prior to the design partition entering user mode.

This problem is scheduled to be addressed in a future release of the Quartus® Prime Pro Edition Software.

Related Products

This article applies to 3 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 GX FPGA

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