Article ID: 000094230 Content Type: Troubleshooting Last Reviewed: 12/09/2024

Why is there an unconstrained clock reported when using the Error Message Register Unloader IP?

Environment

  • Intel® Quartus® Prime Standard Edition
  • Error Message Register Unloader Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 and earlier, you might see an unconstrained clock reported in the Unconstrained Paths Report in the Timing Analyzer as shown below when using the Error Message Register Unloader IP.

    *|altera_emr_unloader:emr_unloader_component|current_state.STATE_CLOCKHIGH

    You will also see critical warning reported during compilation as shown below. This is due to the constraint in the altera_emr_unloader.sdc file that has failed to address the unconstrained clock reported.

    Critical Warning (332049): Ignored create_generated_clock at altera_emr_unloader.sdc(14): Argument <targets> is an empty collection

    Resolution

    To work around this problem in the Quartus® Prime Standard Edition Software version 22.1, follow these steps:

    1. In the altera_emr_unloader.sdc file, comment out line 14. 
    2. Add the create_generated_clock constraint to the altera_emr_unloader.sdc file. For example:

    create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_pins {*|alt_fault_injection_component|alt_fi_inst|*oscillator|clkout}] [get_keepers { *|emr_unloader_component|current_state.STATE_CLOCKHIGH}]

    This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices