Article ID: 000093864 Content Type: Errata Last Reviewed: 11/28/2023

Why doesn't the F-Tile Ethernet Intel® FPGA Hard IP with PTP enabled support the Aldec* Riviera* VHDL simulator in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier, the F-Tile Ethernet Intel® FPGA Hard IP with PTP enabled doesn't support the Aldec* Riviera* VHDL simulator.
    You might get stuck waiting for TX/RX PTP Offset Data Valid assertion when simulating with the Aldec* Riviera* VHDL simulator.

     

     

    Resolution

    There is no workaround for this problem.
    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
     

    Related Products

    This article applies to 2 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

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