Article ID: 000093572 Content Type: Errata Last Reviewed: 11/28/2023

Why doesn't the O-RAN Intel® FPGA IP design example support the Aldec Riviera simulator for the Intel Agilex® device F-Tile in the Intel® Quartus® Prime Pro Edition Software v22.4 and earlier ?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v22.4 and earlier, the O-RAN Intel® FPGA IP design example does not support the Aldec Riviera simulator for the Intel Agilex® device (F-Tile).

    Resolution

    There is no workaround currently.
    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 5 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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