Why does the simulation of the F-tile Serial Lite IV Intel® FPGA IP design with simplex PMA mode fail?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, you may observe that the simulation of the F-Tile Serial Lite IV Intel® FPGA IP design will fail with the following configuration:

• OPN: Intel Agilex® F-tile devices with OPNs that end with the suffix VR0, VR1, and VR2
• Simulation mode: Slowsim
• PMA modulation type: NRZ
• PMA type: FGT
• PMA data rate: 17.4 Gbps
• PMA mode: TX/RX
• Number of PMA lanes: >=14

This problem is due to the clock frequency generated by the simulation model having a high deviation from the expected frequency, which causes FIFO empty or FIFO overflow.

To work around this problem, you can adopt the following two methods:

1. Change the OPN: Intel Agilex® F-tile devices with OPNs that end with the suffix VR3 and AA.
2. Change the simulation mode from Slowsim to Fastsim.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.