Article ID: 000093278 Content Type: Troubleshooting Last Reviewed: 12/02/2024

Why does the simulation of the F-Tile Serial Lite IV FPGA IP design with simplex PMA mode fail?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 22.4, you may observe that the simulation of the F-Tile Serial Lite IV IP design will fail with the following configuration:

  • OPN: Agilex™ F-Tile devices with OPNs that end with the suffix VR0, VR1, and VR2
  • Simulation mode: Slowsim
  • PMA modulation type: NRZ
  • PMA type: FGT
  • PMA data rate: 17.4 Gbps
  • PMA mode: TX/RX
  • Number of PMA lanes: >=14

This problem is due to the clock frequency generated by the simulation model having a high deviation from the expected frequency, which causes FIFO empty or FIFO overflow.

Resolution

To work around this problem, you can adopt the following two methods:

  1. Change the OPN: Agilex F-Tile devices with OPNs that end with the suffix VR3 and AA.
  2. Change the simulation mode from Slowsim to Fastsim.

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