Article ID: 000093262 Content Type: Errata Last Reviewed: 11/22/2024

Why does the O-RAN FPGA IP allow only a single section in one U-plane packet when numprbu = 0?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the O-RAN FPGA IP Webcore version 22.3 and earlier, only a single section is allowed in one U-plane packet when numPrbu = 0.
    The ORAN FPGA IP does not allow multiple sections with numPrbu = 0 in one U-plane packet.

    Resolution

    This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.4.

    Related Products

    This article applies to 7 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 DX FPGA
    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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