Why are there timing violations within the Triple-Speed Ethernet Intel® FPGA IP implemented on the F-Tile of Intel Agilex® 7 FPGA devices?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and earlier, you may see timing violations on the following paths within the Triple-Speed Ethernet Intel® FPGA IP implemented on the F-Tile of Intel Agilex® 7 FPGA devices:

From Node : i_ptp|eth_tse_0|i_tse_pcs_0|alt_mge_pcs20_inst|enc20|enc0|eout_dat[0]                   
To Node : phymac_100g_ftile_auto_tiles|z1577a_x0_y166_n0|hdpldadapt_tx_chnl_23~pld_tx_clk1_dcm.reg

From Node : phymac_100g_ftile_auto_tiles|z1577a_x0_y166_n0|hdpldadapt_rx_chnl_23~pld_rx_clk1_dcm.reg
To Node : i_ptp|eth_tse_0|i_tse_pcs_0|alt_mge_pcs20_inst|rx_datain_reg_sc[5]

A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 22.3. Download and install patch 0.25 from the following links:

• Intel® Quartus® Prime Pro Edition Software v22.3 Patch 0.25 for Windows (.exe) 
• Intel® Quartus® Prime Pro Edition Software v22.3 Patch 0.25 for Linux (.run) 
• Readme for Intel® Quartus® Prime Pro Edition Software v22.3 Patch 0.25 (.txt) 

This issue has been fixed starting with Intel® Quartus® Prime Pro Edition Software version 22.4.