Why is the value of completion data always zero for the CFGRd TLP target to the upstream port in simulation when using the Scalable Switch FPGA IP for PCI Express?

Due to a problem in the Quartus® Prime Pro Edition Software version 22.3 and earlier, completion data for the CFGRd target to the swith upstream port configuration space is always zero in simulation.

To work around this problem, manually edit the Memory Initialization File (MIF) path directory in files with the following steps:

1. Open the file <project_directory>/ip/switch_upstream_port/switch_upstream_port_intel_pcie_sep_ptile_top_0/synth/switch_upstream_port_intel_pcie_sep_ptile_top_0.v.
2. Change the.MIF_DIRECTORY parameter with the project path and MIF location, for example:

.MIF_DIRECTORY (“<project_directory>/ip/switch_upstream_port/ switch_upstream_port_intel_pcie_sep_ptile_top_0/intel_pcie_sep_ptile_top_211/synth/sep/mif”),