Article ID: 000092734 Content Type: Error Messages Last Reviewed: 08/25/2023

Why does compilation failure happen when adding assignments of TX equalization to the F-Tile FGT channel for Intel Agilex® 7 FPGA?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 22.2 or 22.3, a compilation error may occur during Logic Generation with some valid assignments of TX equalization combinations on the F-Tile FGT channel.

    Error example:

    Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings 

    Error(21843): Conflict 0 ---------------------------------------------------------------- 

    Error(21843): Rule: gdra_ip758fluxtop::ux3_txeq_main_tap_relationship_rule @ gdr.z1577a.u_ux_quad_2.flux_top 

    Error(21843):     {(gdr.z1577a.u_ux_quad_2.flux_top.ux3_txeq_main_tap -> IP_INST[0].hw_ip_top|dut|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_tx.txeq_main_tap)+(gdr.z1577a.u_ux_quad_2.flux_top.ux3_txeq_post_tap_1 -> IP_INST[0].hw_ip_top|dut|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_tx.txeq_post_tap_1)+(gdr.z1577a.u_ux_quad_2.flux_top.ux3_txeq_pre_tap_1 -> IP_INST[0].hw_ip_top|dut|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_tx.txeq_pre_tap_1)+gdr.z1577a.u_ux_quad_2.flux_top.ux3_txeq_pre_tap_2<=32'd47} || gdr.z1577a.u_ux_quad_2.flux_top.ux3_powerdown_mode == TRUE 

    Error(21843): Rule: gdra_ip758fluxtop::ux3_txeq_pre_tap_1_range_rule @ gdr.z1577a.u_ux_quad_2.flux_top 

    Error(21843):     gdr.z1577a.u_ux_quad_2.flux_top.ux3_powerdown_mode == FALSE || (gdr.z1577a.u_ux_quad_2.flux_top.ux3_txeq_pre_tap_1 -> IP_INST[0].hw_ip_top|dut|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_tx.txeq_pre_tap_1) == 0 

    Error(21843): Input variables:  

    Error(21843):     user.bb_f_ux_tx[0] -> IP_INST[0].hw_ip_top|dut|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_tx 

    Error(21843):         is_used == TRUE 

    Error(21843):         location == UX11 

    Error(21843):         txeq_main_tap == 40 

    Error(21843):         txeq_post_tap_1 == 13 

    Error(21843):         txeq_pre_tap_1 == 1 

    Error: Design cannot be programmed onto available F-Tiles because given location constraints are conflicting, or because the design requires more resources compared to what is available on current device 

    Error: Quartus Prime Logic Generation Tool was unsuccessful. 14 errors, 0 warnings 

    Error: Peak virtual memory: 12882 megabytes 

    Error: Processing ended: Fri Sep 30 11:22:52 2022 

    Error: Elapsed time: 00:01:49 

    Error: System process ID: 25039 

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 or 22.3, follow the steps below:

    1. Check the TX equalization setting in F-Tile TX Equalizer Tool 

    2. Write equalization value to lane register offset 0x47830


    This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software version 23.1.

     

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series