Article ID: 000092666 Content Type: Troubleshooting Last Reviewed: 09/12/2023

Why does the full calibration simulation of External Memory Interfaces (EMIF) IP example design fail?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® FPGA Simulation Tools
    External Memory Interfaces (EMIF) IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the External Memory Interfaces (EMIF) IP, the simulation of the example design might fail when you set the calibration mode to full calibration.

 

 

Resolution

To work around this problem, follow the steps below:

  1. Open the file <path to the generated example design>/sim/ip/ed_sim/ed_sim_emif_cal/altera_emif_cal_iossm_261/sim/ed_sim_emif_cal_altera_emif_cal_iossm_261_*_arch.sv.
  2. Find the tennm_iossm instantiation in the file.
  3. Change the value of the parameter iossm_use_model to 0, or add a new parameter iossm_use_model with a value of 0 if this parameter does not exist.
    • The parameter section of io_ssm should now look like this:

      tennm_iossm # (
            .gpt_ver                           (SEQ_GPT_GLOBAL_PAR_VER),
            .nios_ver                          (SEQ_GPT_NIOS_C_VER),
            .col_id                            (SEQ_GPT_COLUMN_ID),
            .num_iopacks                       (SEQ_GPT_NUM_IOPACKS),
            .pt_size                           (SEQ_GPT_PARAM_TABLE_SIZE),
            .cal_config                        (SEQ_GPT_GLOBAL_CAL_CONFIG),
            .slave_clk_divider                 (SEQ_GPT_SLAVE_CLK_DIVIDER),
            .nios_clk_freq                     (REMAP_SEQ_GPT_NIOS_CLK_FREQ_KHZ),
            .skip_steps                        (REMAP_SEQ_GPT_GLOBAL_SKIP_STEPS),
            .parameter_table_hex_file          (REMAP_IOSSM_GPT_HEX_FILENAME),

            .abstract_phy                      ("false"),
            .iossm_sim_clk_period_ps           (IOSSM_SIM_NIOS_PERIOD_PS),
            .nios_calibration_code_hex_file    (IOSSM_CODE_HEX_FILENAME),
            .iossm_use_model                   (0)
      ) io_ssm (

  4. Start the simulation again.

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

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