Article ID: 000092498 Content Type: Troubleshooting Last Reviewed: 08/16/2023

Why are the o_clk_rec_div and o_clk_rec_div64 ports improperly constrained when examining the timing reports of the F-tile Ethernet Intel® FPGA Hard IP?


  • Intel® Quartus® Prime Pro Edition

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, the .sdc files generated for the F-tile Ethernet Intel® FPGA Hard IP improperly constrain the o_clk_rec_div and o_clk_rec_div64 ports. These improper constraints can lead to functional failures when using this intellectual property (IP).

    The proper frequency for o_clk_rec_div64 (shown as rx_clkout in the timing reports) is 161.1328125 MHz for 10G and 40G designs and 402.83203125 MHz or 415.0390625 MHz for other rates.

    The proper frequency for o_clk_rec_div (shown as rx_clkout2 in the timing reports)  is 156.25 MHz for 10G, 312.5 MHz for 40G designs, and 390.625 MHz for other rates.



    To work around this problem, it is possible to override the IP-level constraints by defining new clock period constraints in the top-level project Synopsys Design Constraints (SDC) file.

    In the following example, the *rx_pld_pcs_clk_ref and *rx_user_clk_ref clocks are overridden so that rx_clkout and rx_clkout2 frequencies are derived in a clean manner.
    These clocks are the master clocks for rx_clkout and rx_clkout2.

    • set clk_target [get_clock_info -targets IP_INST[0].hw_ip_top|dut|eth_f_0|rx_pld_pcs_clk_ref|ch23]
    • create_clock -add -period 2.095 -name IP_INST[0].hw_ip_top|dut|eth_f_0|rx_pld_pcs_clk_ref|ch23 $clk_target
    • set clk_target [get_clock_info -targets IP_INST[0].hw_ip_top|dut|eth_f_0|rx_user_clk_ref|ch23]
    • create_clock -add -period 2.226 -name IP_INST[0].hw_ip_top|dut|eth_f_0|rx_user_clk_ref|ch23 $clk_target

    This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.4.

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