Error(272006): MGL_INTERNAL_ERROR: Port <altera_syncram_instance_hierarchy> inst altera_syncram_impl1|dffe inst ecc_addr_reg|d has already been assigned

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see this error message during compilation in the synthesis stage for Simple Dual Port RAM when using the following configurations:

· Parameter device_family = "Agilex"

· Parameter ram_block_type = "M20K"

· Parameter enable_ecc = "TRUE"

· Parameter address_aclr_b = "ACLEAR"

· Parameter outdata_reg_b = "CLOCK0/CLOCK1"

· Width x numwords is more than 20480 bits (more than 1 M20K used)

· No read enable signal is used

A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition software version 21.4 and 22.2  

Download and install the patches from the following links:

For Intel® Quartus® Prime Pro Edition Software version 21.4:

• Intel® Quartus® Prime 21.4 Patch 0.60 for Window (.exe)  
• Intel® Quartus® Prime 21.4 Patch 0.60 for Linux (.run)
• Readme for Intel® Quartus® Prime 21.4 Patch 0.60 (.txt) 

For Intel® Quartus® Prime Pro Edition Software version 22.2:

• Intel® Quartus® Prime 22.2 Patch 0.04 for Window (.exe)  
• Intel® Quartus® Prime 22.2 Patch 0.04 for Linux (.run)  
• Readme for Intel® Quartus® Prime 22.2 Patch 0.04 (.txt) 

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3.